module freqdiv50M_50k(clk,clk_out);
	input clk;
	output reg clk_out;
	reg [15:0] counter;

	initial begin
		counter = 0;
		clk_out = 0;
	end

	always @(posedge clk) begin
		if(counter == 16'd1000)
			counter <= 16'd0;
		else if (counter == 16'd500) begin
			clk_out <= ~clk_out;
			counter <= counter + 1;
		end
		else
			counter <= counter + 1;
	end

endmodule